Referenced Items are not available for this document.
In this paper, we present CESTAC, a method to control round-off errors in floating-point scientific computation, based on stochastic arithmetic. The real time use of this method suffers from a bottleneck of software calculations. This paper gives a hardware alternative that would significantly accelerate the computation. The proposed hardware architecture has two parts: a standard floating-point unit (FPU) and a unit dedicated to the control of round-off errors.
Published in:
Electronics, Circuits and Systems, 2002. 9th International Conference on
(Volume:2
)
Date of Conference: 2002
- Page(s):
- 603 - 606 vol.2
- Print ISBN:
- 0-7803-7596-3
- INSPEC Accession Number:
- 7574612
- Digital Object Identifier :
- 10.1109/ICECS.2002.1046241
- Product Type:
- Conference Publications
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