Skip to Main Content
In this paper, we present CESTAC, a method to control round-off errors in floating-point scientific computation, based on stochastic arithmetic. The real time use of this method suffers from a bottleneck of software calculations. This paper gives a hardware alternative that would significantly accelerate the computation. The proposed hardware architecture has two parts: a standard floating-point unit (FPU) and a unit dedicated to the control of round-off errors.
Electronics, Circuits and Systems, 2002. 9th International Conference on (Volume:2 )
Date of Conference: 2002