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Processing time saving in low power voice coding applications using synchronous reconfigurable co-processing architecture

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2 Author(s)
S. M. Carta ; Dept. of Electr. & Electron. Eng., Cagliari Univ., Italy ; L. Raffo

Power dissipation reduction is a stringent constraint in modern mobile devices. It can be obtained by supply voltage or frequency reduction, but a strong reduction of number of cycles for operation must be achieved. To this end, reconfigurable architectures are a valuable solution. In this paper a reconfigurable architecture is designed and successfully tested on GSM coding. An average reduction of 98.2% cycles for specific tasks and of 44.6% cycles for overall computation with respect to standard general purpose processors is obtained.

Published in:

Electronics, Circuits and Systems, 2002. 9th International Conference on  (Volume:2 )

Date of Conference:

2002