Skip to Main Content
A very low-power MPEG-4 video decoder LSI for mobile applications is presented. A 27-MHz 16-b DSP with a vector pipeline architecture, four 27-MHz dedicated hardware engines for accelerating MPEG-4 visual SP@L1 decoding and post video processing, 896 Kb of embedded SRAM for storing reference images and bitstreams, and three peripheral blocks are integrated together on a single chip. The architecture of the DSP is optimized in terms of power consumption and performance. MPEG-4 visual SP@L1 decoding and post-video processing at low operating frequencies are realized using a hybrid architecture consisting of the DSP and the dedicated hardware engines. Clock gating is used extensively to reduce the power consumption of the processor. The processor has high reusability because it does not use process-dependent technology such as VDD-hopping and variable threshold voltages. The chip is implemented using 0.18-μm CMOS technology. Its die area is 37 mm2 and the power consumption is 11 mW at 1.5 V.
Date of Publication: Nov 2002