Referenced Items are not available for this document.
The 3-MB on-chip level three cache in the Itanium 2 processor, built on an 0.18-μm, six-layer Al metal process, employs a subarray design style that efficiently utilizes available area and flexibly adapts to floor plan changes. Through a distributed decoding scheme and compact circuit design and layout, 85% array efficiency was achieved for the subarrays. In addition, various test and reliability features were included. The cache allows for a store and a load every four core cycles and has been characterized to operate above 1.2 GHz at 1.5 V and 110°C. When running at 1.0 GHz, the cache provides a total bandwidth of 64 GB/s.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:37
,
Issue:
11
)
Date of Publication: Nov 2002
- Page(s):
- 1523 - 1529
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 7458926
- Digital Object Identifier :
- 10.1109/JSSC.2002.802354
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 10 December 2002
- Issue Date :
- Nov 2002
- Sponsored by :
- IEEE Solid-State Circuits Society
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