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A 0.25-μm 3.0-V 1T1C 32-Mb nonvolatile ferroelectric RAM with address transition detector and current forcing latch sense amplifier scheme

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10 Author(s)
Mun-Kyu Choi ; Samsung Electron., Kyunggi, South Korea ; Byung-Gil Jeon ; Nakwon Jang ; Byung-Jun Min
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Nonvolatile 32-Mb ferroelectric random access memory (FRAM) with-a 0.25-μm design rule was developed by using an address transition detector (ATD) control scheme for the application to SRAM and applying a common plate folded bit-line cell scheme with current forcing latch sense amplifier (CFLSA) for increasing sensing margin, and adopting a dual bit-line reference voltage generator (DBRVG) for high noise immunity. Compared to a conventional FRAM device, the total chip size is reduced by 10.87%, which was achieved by using a single section data line (SSDL) and removing large gate-oxide capacitors, which is typically used for reference voltage generator for 1T1C FRAM. Furthermore, the imbalance of reference bit-line capacitance and main bit-line capacitance was resolved by using the CFLSA technique.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:37 ,  Issue: 11 )