By Topic

5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

22 Author(s)
Vangal, S. ; Circuits Res., Intel Corp., Hillsboro, OR, USA ; Anders, M.A. ; Borkar, N. ; Seligman, E.
more authors

A 32-bit integer execution core containing a Han-Carlson arithmetic-logic unit (ALU), an 8-entry × 2 ALU instruction scheduler loop and a 32-entry × 32-bit register file is described. In a 130 nm six-metal, dual-VT CMOS technology, the 2.3 mm2 prototype contains 160 K transistors. Measurements demonstrate capability for 5-GHz single-cycle integer execution at 25°C. The single-ended, leakage-tolerant dynamic scheme used in the ALU and scheduler enables up to 9-wide ORs with 23% critical path speed improvement and 40% active leakage power reduction when compared to a conventional Kogge-Stone implementation. On-chip body-bias circuits provide additional performance improvement or leakage tolerance. Stack node preconditioning improves ALU performance by 10%. At 5 GHz, ALU power is 95 mW at 0.95 V and the register file consumes 172 mW at 1.37 V. The ALU performance is scalable to 6.5 GHz at 1.1 V and to 10 GHz at 1.7 V, 25°C.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:37 ,  Issue: 11 )