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The application of adaptive power-supply regulation is extended to serial links. The adaptive supply maximizes the energy-efficiency of the I/O circuits and serves as a global bias to scale the link properties optimally with the bitrate. Parallelism in transceivers and the use of multiphase clocks increase the bitrate to a multiple of the clock frequency and, hence, enable the low frequency low-voltage operation to reduce power while meeting the specified bitrate. Two key designs to enable this power saving are presented: parallelized transceivers for low-voltage operation and dual-loop architecture phase/delay-locked loop for multiphase clock distribution. A prototype chip fabricated in 0.25-μm CMOS process operates at 0.65-5.0 Gb/s while dissipating 9.7-380 mW.