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This paper discusses downlink inner loop power control in UTRA TDD. The current UTRA TDD downlink power control is similar to one in UTRA FDD mode, but due to the time division feature of TDD it can not operate as fast as in FDD and it is affected by rapid changes in environment. In this paper an improvement for the downlink inner loop power control algorithm is presented in which the power control step size is based on the difference between UE measured SIR and target SIR. This difference is then signaled from UE to UTRAN. Since the effectiveness of this algorithm depends on available signaling bandwidth that is used, dynamic system simulations are carried out to find out how many bits are needed for the signaling and how this algorithm is affected by signaling and measurement errors.