A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications

A CMOS local oscillator using a programmable DLL (delay lock loop)-based frequency multiplier to synthesize carrier frequencies from 1.1 GHz to 1.5 GHz is presented. The frequency of the output clock is 7/spl times/ to 10/spl times/ of an input reference clock. No LC-tank is used in the proposed design, such that the power dissipation as well as the active area are drastically reduced. The design is carried out using the TSMC 1P5M 0.25 /spl mu/m CMOS process at 2.5 V power supply. The average lock time is optimally shortened by initializing the start-up voltage of the VCDTL (voltage-controlled delay tap line) at the mid point of the working range. Meanwhile, the power dissipation of the physical chip measures only 52.2 mW at 1.2 GHz output.