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A 10-bit, current-steering, high-speed CMOS D/A converter is presented using a delay technique to increase the speed of the converter. Simulation results show that the spurious-free-dynamic-range (SFDR) is better than 62 dB for sampling frequency up to 400 MSample/s and signals from DC to Nyquist. Monte-Carlo simulations show that differential non-linearity (DNL) and integral non-linearity (INL) are better than 0.03 least significant bit (LSB) and 0.24 LSB, respectively. The estimated INL-yield is 99.7% and the design is based on it. The converter dissipates less than 250 mW from a 3 V power supply when operating at 400 MHz. The circuit has been designed in a standard 0.6 μm-CMOS process. The results have been checked with all process corners from -40°C to 85°C and power supply from 2.7 V to 3.3 V.