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This paper proposes a new method which offers a high level of synchronization between a source, which is primarily digital, that generates a test signal and the analog-to-digital converter (ADC) that will sample it. By using a single clock to control the source, a clock divider may be used to derive a clock that will trigger an ADC at the appropriate times to produce a coherently sampled data set. Thus, the timing of the waveform and the ADC will be accurately synchronized; moreover, since test time is a valuable commodity, a predictable number of clock cycles can be issued in order to generate a sampled data set. A computer simulation is given which fully characterizes the theoretical aspects of this paper. In addition, selected laboratory measurements are also given for discussion.