A voltage reference compatible with standard SOI CMOS processes and consuming 1 pA to 50 nA from room temperature up to 300/spl deg/C

Summary form only given. We have presented a new and simple implementation of a voltage reference, based on an optimal standard SOI process mask use and a new architecture. The voltage drift over temperature is similar to standard references implementation while the power consumption and the chip area are drastically reduced. Additional threshold voltages can be obtained at no cost on most SOI processes and can be even more exploited for their usefulness in analog applications. Moreover, intrinsic MOSFETs, having better matching properties compared to doped devices, are of a great utility for critical analog blocks.