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Fringing-induced barrier lowering (FIBL) effects of 100 nm FD SOI NMOS devices with high permittivity gate dielectrics and LDD/sidewall oxide spacer

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2 Author(s)
Lin, S.C. ; Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada ; Kuo, J.B.

This paper reports the fringing-induced barrier lowering (FIBL) effects of 100 nm FD SOI NMOS devices with high permittivity gate dielectrics and LDD/sidewall oxide spacer structure. Based on the study, with a higher k gate dielectric, the subthreshold slope is less steep due to the reduced potential barrier in the surface channel caused by a larger vertical electric field in the LDD region under the sidewall oxide spacer next to the drain.

Published in:

SOI Conference, IEEE International 2002

Date of Conference:

7-10 Oct 2002