Scaling assessment of fully-depleted SOI technology at the 30 nm gate length generation

Thin-film SOI MOSFETs are of interest for scaling devices down into the deep-submicron region due to their ability to reduce short-channel effects (SCE). While double-gate MOSFET is currently considered the most promising candidate for CMOS scaled beyond the 20-30nm limit, we investigate the single-gated SOI MOSFET scalability at the 30nm gate length generation. We have examined their electrostatic behavior using the drift-diffusion ISE DESSIS device simulator. An internally developed quantum transport simulator was also used to confirm the DESSIS simulation trend and assess the impact of thin silicon film on SCE. The device under study has mid-gap workfunction gate material, undoped channel and 15/spl Aring/ gate oxide thickness. This device presents the strongest scaling potential due to the high mobility from the absence of ionized doping impurities, suppression of dopant fluctuation effects and reduced threshold voltage variation with silicon film thickness. We have studied the impact of the silicon film thickness, BOX and front gate dielectric thickness and k values on the short-channel performance of the device. The ground plane structure was also simulated for comparison. We show that extremely thin silicon film thickness around 3nm would be necessary to meet the low-power applications 1999 ITRS specifications at the 50nm technology node. The quantum mechanical effects at this silicon film thickness become dominant, preventing the FDSOI technology to be scaled down to 30nm and beyond.