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Performance assessment of scaled strained-Si channel-on-insulator (SSOI) CMOS

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4 Author(s)
Keunwoo Kim ; IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA ; Ching-Te Chuang ; K. Rim ; R. V. Joshi

Strained-Si channel devices have recently become of interest for future high-performance applications due to higher carrier mobility and preservation of conventional device structure/geometry. One important feature in the strained-Si devices is the heterostructural band offset in the channel and buffer layer, which reduces Vt, thereby increasing Ioff. We assess the circuit performance of strained-Si devices including SSOI via a physics-based circuit model calibrated against fabricated 70 nm strained and unstrained (control) devices. Device design point and performance projection and trade-off are presented, thus allowing exploitation of maximum performance in the strained-Si devices.

Published in:

SOI Conference, IEEE International 2002

Date of Conference:

7-10 Oct 2002