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Efficient construction of aliasing-free compaction circuitry

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2 Author(s)
Sinanoglu, O. ; Comput. Sci. & Eng. Dept., Univ. of California, San Diego, CA, USA ; Orailoglu, A.

Parallel testing of cores can reduce SOC test times, but the finite number of chip I/Os limits such parallelism. Space and time compaction can maximize the required test bandwidth at the core outputs. Our proposed space and time compaction methodology guarantees a single-bit bandwidth, enabling the test of cores through the allocation of fewer chip pin-outs. In this way, our scheme maximizes parallelism among core tests

Published in:

Micro, IEEE  (Volume:22 ,  Issue: 5 )

Date of Publication:

Sep/Oct 2002

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