A hierarchical test methodology for systems on chip

We present a hierarchical test methodology for testing a SOC with heterogeneous cores, including the 1149.1-wrapped, P1500-wrapped, and BIST memory cores. We propose an 1149.1-based hierarchical test manager that also provides P1500 test control signals. This scheme includes a memory BIST interface, providing both serial and parallel access ports for BIST circuits. Our approach offers low area and pin overhead, and high flexibility.