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Coping with latency in SOC design

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2 Author(s)
Carloni, L.P. ; California Univ., Berkeley, CA, USA ; Sangiovanni-Vincentelli, A.L.

Latency-insensitive design is the foundation of a correct-by-construction methodology for SOC design. This approach can handle latency's increasing impact on deep-submicron technologies and facilitate the reuse of intellectual-property cores for building complex systems on chips, reducing the number of costly iterations in the design process

Published in:

Micro, IEEE  (Volume:22 ,  Issue: 5 )