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Chain: a delay-insensitive chip area interconnect

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2 Author(s)
Bainbridge, J. ; Dept. of Comput. Sci., Manchester Univ., UK ; Furber, S.

The increasing complexity of system-on-a-chip designs exposes the limits imposed by the standard synchronous bus. The authors propose a mixed system as a solution.

Published in:

Micro, IEEE  (Volume:22 ,  Issue: 5 )