Skip to Main Content
This paper proposes a power profile manipulation approach which merges two distinct research directions in low power testing: minimization of test power dissipation and test application time reduction under power constraints. It is shown how complementary techniques can be easily combined through this approach to significantly increase test concurrency under power constraints. This is achieved in two steps: in the first step power dissipation is considered a design objective and, consequently, it is minimized; results are further exploited in the second step, when power becomes a design constraint under which the test application time is reduced. A distinctive feature of the proposed power profile manipulation approach is that it can be included in, and consequently improve, any existing power constrained test scheduling algorithm. Extensive experimental results using benchmark circuits, considering test-per-clock, as well as test-per-scan schemes, show that by integrating the proposed power profile manipulation approach into any existing power constrained test scheduling algorithm, savings up to 41 % in test application time are achieved.