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A new NMOS layout structure for radiation tolerance

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3 Author(s)
Snoeys, W.J. ; EP Div., CERN, Geneva, Switzerland ; Gutierrez, T.A.P. ; Anelli, G.

A new transistor structure is presented to obtain radiation tolerance in commercial submicron CMOS technology without any process modifications. The NMOS transistor and field leakage normally induced by ionizing irradiation is remedied by acting on the work function of the transistor gate at the transistor edges. The technique also works in a CMOS process where transistor source and drains are silicided. Contrary to the enclosed layout transistor (ELT) previously proposed for this purpose, this new transistor structure does not limit the transistor width over transistor length (W/L) ratios to large values and thereby eliminates one of the most stringent constraints in the design of radiation tolerant circuits in standard CMOS. Measurements on fabricated devices demonstrate the functionality of the transistor structure and its radiation tolerance up to 40 Mrad(SiO2).

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Nuclear Science, IEEE Transactions on  (Volume:49 ,  Issue: 4 )