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Analysis of 1/f noise in CMOS preamplifier with CDS circuit

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6 Author(s)
Tae-Hoon Lee ; Dept. of Nucl. & Quantum Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea ; Gyuseong Cho ; Hee Joon Kim ; Seung Wook Lee
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The noise of a CMOS charge-sensitive preamplifier (CSA) and correlated double sample-and-hold (CDS) circuit matching a capacitive source is calculated to analyze the relative portions of thermal and 1/f noise. In most radiation detector systems, a PMOS transistor is used as the input device because its 1/f noise is lower than that of the NMOS. However, to study the 1/f noise reduction action of a CDS circuit in the 1/f noise dominant condition, an NMOS transistor is deliberately chosen as the input transistor of the CSA. The theoretical minimum number of equivalent noise charge (ENC) that can be achieved in this system is about 1700 electrons rms for a 5-pF detector capacitance. To demonstrate the theoretical analysis, a chip of CSA and CDS was designed in a 0.5-μm CMOS technology. The main amplifier is a differential input single-ended folded cascode, and its measured gain bandwidth is more than 5 MHz. The measured ENCs of the CSA shaper and the CSA-CDS systems are 2105 and 3046 electrons rms, respectively.

Published in:

Nuclear Science, IEEE Transactions on  (Volume:49 ,  Issue: 4 )

Date of Publication:

Aug 2002

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