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Reduced computational redundancy implementation of DSP algorithms using computation sharing vector scaling

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2 Author(s)
K. Muhammad ; Texas Instrum. Inc., Dallas, TX, USA ; K. Roy

In this paper, we present a general approach which specifically targets reduction of redundant computation in common digital-signal processing (DSP) tasks such as filtering and matrix multiplication. We show that such tasks can be expressed as multiplication of vectors by scalars and this allows fast multiplication by sharing computation. Vector scaling operation is decomposed to find the most effective precomputations which yield a fast multiplier implementation. Two decomposition approaches are presented, one based on a greedy decomposition and the other based on fixed-size lookup and this leads to two multiplier architectures for vector-scalar products. Analog simulation of an example multiplier shows a speed advantage by a factor of about 1.85 over a conventional carry save array multiplier. Further simulations using 0.18 /spl mu/ technology show up to 20% speed advantage over Booth encoded Wallace tree multipliers.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:10 ,  Issue: 3 )