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Microarchitecture-level power management

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2 Author(s)
A. Iyer ; AMD, Austin, TX, USA ; D. Marculescu

In this paper, we present a strategy for run-time profiling to optimize the configuration of a superscalar microprocessor dynamically so as to save power with minimum-performance penalty. The configuration of the processor is changed according to the parallelism and power profile of the running application. To identify the optimal configuration, additional hardware with minimal overhead is used to detect the parts of the running application which have good potential for energy savings. Experiments on some benchmark programs show good savings in total energy consumption; we have observed a mean decrease of 18% in average power, and 9% in total energy. Our proposed approach can be used for energy-aware computing in either portable applications or in desktop environments where power density is becoming a concern. This approach can also be incorporated in power-management strategies like advanced configuration and power interface (ACPI) as a replacement for classic thermal management schemes such as static-clock throttling. Our approach is shown to be better than static-throttling methods presently used in power management.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:10 ,  Issue: 3 )