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The question really comes back to the sufficiency of the quality provided by scan patterns on today's microprocessors. State-of-the-art microprocessor designs and manufacturing processes are always pushing the envelope. This aggressive posture with respect to the underlying technology is one cause of the demise of the stuck-at fault model and its cousins. ATPG is only as good as its fault model. Scan has less utility for testing some of the very analog features of today's microprocessors such as gigabyte/sec differential busses. Though scan has been used in the past for I/O timing spec and speed bin testing, this is less applicable than it once was because the silicon is so much faster than the ATE. I recommend using best at-speed scan, ATPG, and BIST practices to achieve quantifiably high fault coverage, and also performing functional sequences under stress conditions.