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A 300-MPOS video signal processor with a parallel architecture

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6 Author(s)
Minami, T. ; NTT LSI Lab., of Kanagawa, Japan ; Kasai, R. ; Yamauchi, Hironori ; Tashiro, Y.
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A 300-MOPS image digital signal processor (IDSP) including four pipelined date processing units and three parallel input-output (I/O) ports has been developed using a 0.8-μm BiCMOS technology. The IDSP integrates 910000 transistors in a 15.2-mm×15.2-mm area using a macrocell-oriented building-block design environment. The power dissipation was reduced to 1.0 W per 25-MHz instruction cycle, and a TTL-compatible I/O interface was retained by implementing two power supplies-one providing 3 V and the other 5 V. With this performance, a single-board 64/128-kb/s video codec was implemented with four IDSPs

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:26 ,  Issue: 12 )

Date of Publication:

Dec 1991

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