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Fast and efficient algorithm for the multiplierless realisation of linear DSP transforms

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2 Author(s)
Yurdakul, A. ; Dept. of Comput. Eng., Bogazici Univ., Istanbul, Turkey ; Dundar, G.

A fast algorithm having a pseudopolynomial run-time and memory requirement in the worst case is developed to generate multiplierless architectures at all wordlengths for constant multiplications in linear DSP transforms. It is also re-emphasised that indefinitely reducing operators for multiplierless architectures is not sufficient to reduce the final chip area. For a major reduction, techniques like resource folding must be used. Simple techniques for improving the results are also presented

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Circuits, Devices and Systems, IEE Proceedings -  (Volume:149 ,  Issue: 4 )