Scheduled System Maintenance:
Some services will be unavailable Sunday, March 29th through Monday, March 30th. We apologize for the inconvenience.
By Topic

Digital beamforming techniques and processors based on quadratic residue number system techniques

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Langston, J.L. ; Texas Instrum. Inc., Dallas, TX, USA ; Hinman, K.

A very-high-performance digital beamforming processor has been implemented using ASICs (application-specific integrated circuits) fabricated in readily available commercial CMOS process technology by using QRNS (quadratic residue number system) techniques. The chips have been designed and tested to operate at 50 MHz. The brassboard processor is capable of providing either four simultaneous beams, each with a bandwidth of 20 MHz, or 32 simultaneous beams, each with a bandwidth of 2 MHz. The brassboard system is capable of supporting 64 channels of 9-b I and 9-b Q digitized data and weights, but the architecture can support up to 512 channels of 14-b I and 14-b Q digitized data and weights. This demonstrates the feasibility of digital beamforming using silicon technology

Published in:

Military Communications Conference, 1989. MILCOM '89. Conference Record. Bridging the Gap. Interoperability, Survivability, Security., 1989 IEEE

Date of Conference:

15-18 Oct 1989