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The parasitic bipolar amplification of silicon on insulator (SOI) devices is analyzed as a function of the technology integration from 0.8 μm down to 0.1 μm. Experiments and simulations show that the bipolar gain does not increase with technology downscaling. The body tie efficiency, to reduce the bipolar amplification, is measured on both transistors and circuits. Implications on the dose rate hardness are deduced on registers with and without body ties as a function of the SOI technology integration.