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Architecture and hardware for scheduling gigabit packet streams

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4 Author(s)
Krishnamurthy, R. ; Center for Exp. Res. in Comput. Syst., Georgia Inst. of Technol., Atlanta, GA, USA ; Yalamanchill, S. ; Schwan, K. ; West, R.

We present an architecture and hardware for scheduling gigabit packet streams in server clusters that combines a network processor datapath and an FPGA for use in server NICs and server cluster switches. Our architectural framework can provide EDF static-priority, fair-share and DWCS native scheduling support for best effort and real-time streams. This allows (i) interoperability of scheduling hardware supporting different scheduling disciplines and (ii) helps in providing customized scheduling solutions in server clusters based on traffic type, stream content, stream volume and cluster hardware using a hardware implementation of a scheduler running at wire-speeds. The architecture scales easily from 4 to 32 streams on a single Xilinx Virtex 1000 chip and can support 64-byte 1500-byte Ethernet frames on a 1 Gbps link and 1500-byte Ethernet frames on a 10 Gbps link. A running hardware prototype of a stream scheduler in a Virtex 1000 PCI card can divide the bandwidth based on user specifications and meet the temporal bounds and packet-time requirements of multi-gigabit links.

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High Performance Interconnects, 2002. Proceedings. 10th Symposium on

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