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1.5-V single work-function W/WN/n/sup +/-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM

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19 Author(s)
Rengarajan, R. ; Microelectron. Semicond. Res. & Dev. Center, IBM Corp., Hopewell Junction, NY, USA ; Boyong He ; Ransom, C. ; Chang Ju Choi
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This letter reports on 1.5-V single work-function W/WN/n/sup +/-poly gate CMOS transistors for high-performance stand-alone dynamic random access memory (DRAM) and low-cost low-leakage embedded DRAM applications. At VDD Of 1.5-V and 25/spl deg/C, drive currents of 634 μA/μm for 90-nm L/sub gate/ NMOS and 208 μA-μm for 110-nm L/sub gate/ buried-channel PMOS are achieved at 25 pA/μm off-state leakage. Device performance of this single work function technology is comparable to published low leakage 1.5-V dual work-function technologies and 25% better than previously reported 1.8-V single work-function technology. Data illustrating hot-carrier immunity of these devices under high electric fields is also presented. Scalability of single work-function CMOS device design for the 90-nm DRAM generation is demonstrated.

Published in:

Electron Device Letters, IEEE  (Volume:23 ,  Issue: 10 )