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Implementation of fully self-aligned bottom-gate MOS transistor

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6 Author(s)
Shengdong Zhang ; Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., China ; Ruqi Han ; Zhikuan Zhang ; Ru Huang
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This letter reports the implementation of a bottom-gate MOSFET, which possesses the following fully self-aligned structural features: 1) self-aligned source-drain to bottom-gate; 2) self-aligned thick source-drain and thin channel; and 3) self-aligned and mask-free lightly doped drain (LDD). The complete self-alignment is realized by combining a conventional ion implantation and a subsequent chemical-mechanical polishing (CMP) step. The process is applied to poly-Si films crystallized from an a-Si film deposited by LPCVD using a metal-induced unilateral crystallization technique, and is grain-enhanced further in a high temperature annealing step. Deep submicron fully self-aligned bottom-gate pMOS transistors with channel length less than 0.5 μm are fabricated. The measured performance parameters include threshold voltage of -0.43 V, subthreshold swing of 113 mV/dec, effective hole mobility of 147 cm2/V-s, off-current of 0.17 pA/μm, and on-off current ratio of 7.1×10/sup 8/.

Published in:

Electron Device Letters, IEEE  (Volume:23 ,  Issue: 10 )