By Topic

One structure for fractional delay filter with small number of multipliers

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $33
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
G. Jovanovic-Dolecek ; Dept. of Electron., INAOE, Puebla, Mexico ; J. Diaz-Carmona

A wide-bandwidth, high-resolution fractional delay filter (FDF) structure with a small number of multipliers per output sample and a short coefficient computing time is presented. The proposal is based on the use of a frequency FDF design method up to only half of the Nyquist frequency, in a multirate structure

Published in:

Electronics Letters  (Volume:38 ,  Issue: 19 )