New DRAM noise generation under half Vcc precharge and its reduction using a transposed amplifier

Recently, DRAM data line interference noise generated during amplification was reported as the key problem to designing DRAMS of 16Mb and beyond. However, the detailed noise generation mechanism and its reduction remained unknown. especially when employing the most important circuit technique such as half Vcc precharge using CMOS sense amp. In this paper, three new achievements are described. First, in half Vcc precharge approach specific combinations of memory cell reading information and operating sequence of NMOS and PMOS amps, composing the CMOS amp, cause data line interference noise during amplification. Second, there also exists interference noise from some part of a CMOS amp. Third, the noise results in a detrimental effect On data holding time characteristics