Improvement of soft error rate in MOS SRAMs

Recently, the access time of VLSI CMOS SRAMS 1,2,3 has come to the level of ECL RAMs. The a-particle induced soft error in the SRAMs with high resistive load cell has been a serious problem, bc cause the soft error rate (SER) abruptly increases at the short cycle time. Although the SER is reduced by the increases of the capacitance in storage nodes, the scaled small cell area limits the increase of the capacitance. This paper proposes two unique improvement techniques with no extra silicon area, and the SER is improved by 2 orders of magnitude.