A 7.5ns 32K x 8 high-speed CMOS SRAM

This paper rill describe a 256K(32Kx8) CHOS SRAIl which achieved an access time of 7.50s and "A active current at 501z operation. High speed access and low power dissipation are achieved through innovative circuits such as a 32-block architecture. Double Activated Pulse circuit and data output reset circuit. This RM has been fabricated in a 0.8 μm CUOS technology.