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An adaptive Reed-Solomon (RS) decoder is designed, which can decode RS codes of any block length n as well as any message length k. This unique feature is favorable for a shortened RS code, since it eliminates the need to insert zeros before decoding the code. Furthermore, the value of error-correcting capability t can be changed at every codeword block. The decoder permits 4-step pipelined processing based on the modified Euclid's algorithm (MEA). Each step has a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for varying values of t. The operating length of the shift registers shortened by one can be adjusted to be varied according to the different values of t. To maintain the throughput rate with less circuitry, the MEA block uses both the multiplexing and recursive technique and the overclocking technique. The adaptive RS decoder over GF(28) having the error-correcting capability of up to 10 has been designed in VHDL, and successfully synthesized in a FPGA chip.