By Topic

Design of radiation tolerant CMOS APS system-on-a-chip image sensors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
El-Sayed Eid ; Photobit Technol. Corp., Pasadena, CA, USA ; Ay, S.U. ; Fossum, E.R.

A methodology for designing radiation tolerant CMOS APS SOC image sensors is presented. It is based on the experimental results of test chips that had been designed, fabricated, and characterized. Details of the basic building blocks of a proposed design are presented. The proposed design is in a 0.35-μm CMOS standard process. The radiation tolerance level could be up to 30 Mrad (Si) total dose of ionizing radiation. The proposed methodology has the potential of yielding highly integrated, highly functional, highly compact, low power, radiation tolerant, cost effective CMOS APS SOC image sensors.

Published in:

Aerospace Conference Proceedings, 2002. IEEE  (Volume:4 )

Date of Conference:

2002