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A 120-mW 3-D rendering engine with 6-Mb embedded DRAM and 3.2-GB/s runtime reconfigurable bus for PDA chip

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5 Author(s)
Woo, R. ; Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea ; Chi-Weon Yoon ; Jeonghoon Kook ; Se-Joong Lee
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A low-power three-dimensional (3-D) rendering engine is implemented as part of a mobile personal digital assistant (PDA) chip. Six-megabit embedded DRAM macros attached to 8-pixel-parallel rendering logic are logically localized with a 3.2-GB/s runtime reconfigurable bus, reducing the area by 25% compared with conventional local frame-buffer architectures. The low power consumption is achieved by polygon-dependent access to the embedded DRAM macros with line-block mapping providing read-modify-write data transaction. The 3-D rendering engine with 2.22-Mpolygons/s drawing speed was fabricated using 0.18-μm CMOS embedded memory logic technology. Its area is 24 mm2 and its power consumption is 120 mW.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:37 ,  Issue: 10 )

Date of Publication:

Oct 2002

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