Skip to Main Content
The proposed pulsewidth control loop (PWCL) adopts the same architecture as the conventional PWCL, but with a new duty-cycle detector and a new pulse generator. Using the new building block circuits, the clock frequency can be increased tremendously, and the output of the PWCL has fixed rising edge, which will not disturb the phase-locking result by a preceding phase-locked loop (PLL) or delay-locked loop (DLL). This means that the clock buffer can include a PLL/DLL and a PWCL to perform phase locking as well as pulsewidth adjustment simultaneously. All the building blocks used in the new PWCL have simple circuit structures that are suitable for low-voltage operation. A test chip is implemented in a 0.35-μm CMOS process with only 1.8-V VDD successfully generates a clock signal with a 0.6-ns pulsewidth for a heavily pipelined multiplier to operate at 400 MHz. The features of operating at low voltage, providing variable duty cycle, and being able to cooperate with PLL/DLL make the new PWCL suitable for system-on-chip (SOC) applications.