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A low-power segmented nonlinear DAC-based direct digital frequency synthesizer

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2 Author(s)
Jiandong Jiang ; Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA ; E. K. F. Lee

A 2.5-V CMOS direct digital frequency synthesizer (DDFS) with 12 bits of phase resolution and 11 bits of amplitude resolution is presented. Low power consumption is achieved using a nonlinear digital-to-analog converter (DAC). To further reduce power and area, a new technique is proposed to segment the non-linear DAC into a coarse nonlinear DAC and a number of fine nonlinear sub-DACs. The DDFS fabricated in a 0.25-μm CMOS process occupies an active area of 1.4 mm2. For a clock frequency of 300 MHz, it consumes 240 mW and the spurious-free dynamic range is less than 51 dB for output frequencies up to 3/8 of the clock frequency.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:37 ,  Issue: 10 )