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Switched-current circuits in digital CMOS technology with low charge-injection errors

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2 Author(s)
Balachandran, G.K. ; Analog Devices, Raleigh, NC, USA ; Allen, P.E.

In this paper, digital CMOS switched-current (SI) circuits with low charge-injection errors are presented. These circuits are based on the operation of the switches at virtual-ground nodes to result in signal-independent charge injection. Based on this scheme, different topologies for the memory cell are discussed. To verify the theoretical concepts developed, a third-order elliptic low-pass SI filter is implemented in a 0.25-μm digital CMOS process. The filter nominally operates with a clock frequency of 10 MHz, cutoff frequency of 1 MHz, and a power supply of 2.3 V, while consuming 29 mW of power and processing input signals as large as 600-μA peak differential. The low-charge injection nature of the circuit is reflected in its low total harmonic distortion of -59 dB for a 0.3-MHz signal with a modulation index of 0.5.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:37 ,  Issue: 10 )