By Topic

Switched-current circuits in digital CMOS technology with low charge-injection errors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Balachandran, G.K. ; Analog Devices, Raleigh, NC, USA ; Allen, P.E.

In this paper, digital CMOS switched-current (SI) circuits with low charge-injection errors are presented. These circuits are based on the operation of the switches at virtual-ground nodes to result in signal-independent charge injection. Based on this scheme, different topologies for the memory cell are discussed. To verify the theoretical concepts developed, a third-order elliptic low-pass SI filter is implemented in a 0.25-μm digital CMOS process. The filter nominally operates with a clock frequency of 10 MHz, cutoff frequency of 1 MHz, and a power supply of 2.3 V, while consuming 29 mW of power and processing input signals as large as 600-μA peak differential. The low-charge injection nature of the circuit is reflected in its low total harmonic distortion of -59 dB for a 0.3-MHz signal with a modulation index of 0.5.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:37 ,  Issue: 10 )