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A 1-V 10.7-MHz switched-opamp bandpass ΣΔ modulator using double-sampling finite-gain-compensation technique

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3 Author(s)
Cheung, V.S.L. ; Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China ; Luong, H.C. ; Wing-Hung Ki

A 1 V switched-capacitor (SC) bandpass sigma-delta (ΣΔ) modulator is realized using a high-speed switched-opamp (SO) technique with a sampling frequency of up to 50 MHz, which is improved ten times more than prior 1 V SO designs and comparable to the performance of the state-of-the-art SC circuits that operate at much higher supply voltages. On the system level, a fast-settling double-sampling SC biquadratic filter architecture is proposed to achieve high-speed operation. A low-voltage double-sampling finite-gain-compensation technique is employed to realize a high-resolution ΣΔ modulator using only low-DC-gain opamps to maximize the speed and to reduce power dissipation. On the circuit level, a fast-switching methodology is proposed for the design of the switchable opamps to achieve a switching frequency up to 50 MHz. Implemented in a 0.35-μm CMOS process (VTP=0.82 V and VTN=0.65 V) and at 1 V supply, the modulator achieves a measured peak signal-to-noise-and-distortion ratio (SNDR) of 42.3 dB at 10.7 MHz with a signal bandwidth of 200 kHz, while dissipating 12 mW and occupying a chip area of 1.3 mm2.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:37 ,  Issue: 10 )