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Low power CMOS level shifters by bootstrapping technique

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2 Author(s)
S. C. Tan ; Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore ; X. W. Sun

A level shifter circuit using bootstrapped gate drive to minimise voltage swing is presented. Capacitors are used to maintain the voltage difference between the gates of pull-up PMOS and pull-down NMOS. The power saving over conventional level shifter is typically 50% for a 5 V input and 12 V output

Published in:

Electronics Letters  (Volume:38 ,  Issue: 16 )