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High defect coverage with low-power test sequences in a BIST environment

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5 Author(s)
Girard, P. ; Microelectron. Dept., LIRMM, Montpellier, France ; Landrault, C. ; Pravossoudovitch, S. ; Virazel, A.
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A new technique, random single-input change (RSIC) test generation, generates low-power test patterns that provide a high level of defect coverage during low-power BIST of digital circuits. The authors propose a parallel BIST implementation of the RSIC generator and analyze its area-overhead impact

Published in:

Design & Test of Computers, IEEE  (Volume:19 ,  Issue: 5 )