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Clock duty cycle adjuster circuit for switched capacitor circuits

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1 Author(s)
Karthikeyan, S. ; Texas Instrum. Inc., Dallas, TX, USA

A pulse width locked loop, which can be used to generate an output clock with a wide range of duty cycle (25 to 75%) precisely, from a single-ended input clock with any duty cycle (25 to 75%) is explained. Measurement results of an application of this loop, in pipelined data converters, are reported

Published in:

Electronics Letters  (Volume:38 ,  Issue: 18 )