Referenced Items are not available for this document.
A pulse width locked loop, which can be used to generate an output clock with a wide range of duty cycle (25 to 75%) precisely, from a single-ended input clock with any duty cycle (25 to 75%) is explained. Measurement results of an application of this loop, in pipelined data converters, are reported
Published in:
Electronics Letters
(Volume:38
,
Issue:
18
)
Date of Publication: 29 Aug 2002
- Page(s):
- 1008 - 1009
- ISSN :
- 0013-5194
- INSPEC Accession Number:
- 7389735
- Digital Object Identifier :
- 10.1049/el:20020657
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 07 November 2002
- Issue Date :
- 29 Aug 2002
- Sponsored by :
- Institution of Engineering and Technology
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