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This paper proposes an efficient algorithm for extracting SPICE-compatible circuits of embedded interconnect structures from FDTD-simulated time-domain reflections. A layer-peeling technique (LPT) is first employed to de-embed the interconnect-under-extract (IUE) and obtain the time-domain response of the IUE itself. A general pencil of matrix method (GPOM) is then used to get the pole-residue representation of the time-domain response of the IUE. A pole-reducing procedure is implemented based on a bandwidth criterion to obtain another pole-residue representation with minimum poles. Finally, the lumped equivalent models of the IUE are synthesized by an equivalent lumped-model extraction technique, in which four types of equivalent model bases are used. The equivalent circuit can be easily implemented in a SPICE-like simulator. A bonding wire structure and a multiple discontinuous microstrip line are presented as an example to demonstrate the validity of the proposed algorithm both in time and frequency domains.