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In this paper the problem of software simulation of the noise distribution in the chip has been considered. On the basis of earlier developed analytical equations the internal electromagnetic noise distribution in the chip with orthogonal and complanar topology of power supply feed have been obtained. These results can be useful to estimate the trends of the EM noise in the chip and evaluate the most critical area. Further, the developer can change the placing of the functional modules in the chip to increase the stability of the designed device to internal noises.