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Due to the rapid scaling of the CMOS process, the fringing capacitance and the coupling capacitance will play a major role in the noise analysis of the integrated circuits. Coupling induced signal integrity problems will also become more acute. Crosstalk may cause false triggering, improper logic levels, and increased delay or race conditions. In this work, the authors propose a methodology for buffer insertion to reduce on-chip coupling and to achieve timing constraints and requirements.