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Fast locking delay-locked loop using initial delay measurement

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3 Author(s)
Taesung Kim ; Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., YuseongGu, South Korea ; Sung Ho Wang ; Beomsup Kim

A delay-locked loop (DLL) architecture capable of incorporating fast locking and low jitter features simultaneously is reported. A test chip was fabricated in a 0.6 μm CMOS process to prove its functionality. The proposed DLL can align the internal clock to the external reference clock within two cycles and maintain its locking state with the aid of feedback operation

Published in:

Electronics Letters  (Volume:38 ,  Issue: 17 )